1. Field of the Invention
The present invention relates to a fabrication method for an integrate circuit. More particularly, the present invention relates to a fabrication method for a shallow trench isolation structure.
2. Description of the Related Art
Isolation structures formed in an integrated circuit are for the purpose to prevent carriers from penetrating through the substrate to neighboring devices. Electronic devices such as the metal oxide semiconductor field-effect transistor (MOSFET) are separated from each other by isolation structures to reduce a charge leakage. During the fabrication for the Very Large Scale Integration and the Ultra Large Scale Integration, the density of transistors is significantly increased. In order to prevent a short circuit between the neighboring transistor devices, isolation structures must form between the transistor devices. As the integration of a device continues to increase while the line width decreases as in the 0.25 deep sub-micron manufacturing, shallow trench isolation structures are formed to isolate the neighboring devices.
The conventional shallow trench isolation structure is formed by using anisotropic etching to form a trench in the substrate, followed by performing thermal oxidation to form a liner oxide layer on the exposed substrate surface. A non-doped oxide layer is then formed filling the trench, followed by a densification process and other processes to complete the formation of the device isolation structure.
FIGS. 1A to 1D are schematic, cross-sectional views showing the manufacturing of a shallow trench isolation structure according to the conventional practice. As shown in FIG. 1A, a pad oxide layer 102 and a silicon nitride layer 104 are formed on a semiconductor substrate 100. The silicon nitride layer 104 serves as a mask layer and to provide a barrier function.
Referring to FIG. 1B, the semiconductor substrate 100 is then defined to form a shallow trench 106. An oxide layer is then formed on the silicon nitride layer 104 and filling the shallow trench 106, followed by performing chemical mechanical polishing to form the oxide layer 108 in the trench as shown in FIG. 1C. The silicon nitride layer 104 is to provide a barrier function in the chemical mechanical polishing process.
Continuing to FIG. 1D, the silicon nitride layer 104 and the pad oxide layer 102 are removed to complete the fabrication of a shallow trench isolation structure. During the removal of the silicon nitride layer 104 and the pad oxide layer 102, especially in the removal of the pad oxide layer 102, the oxide layer 108 formed in the shallow trench is also being etched due to a partial exposure to the etchant. The edge 110 between the pad oxide layer 102 and the substrate 100 would form an irregular profile, exposing a corner of the substrate 100.
Since the properties of silicon nitride and oxide are different, for example different expansion coefficients, stress is generated and accumulated in the substrate during the formation of the shallow trench isolation structure. Furthermore, after the formation of the shallow trench isolation structure, an N-type or a P-type ion is implanted in the substrate to provide a conductive state in the substrate. During the ion implantation process, the ion bombardment on the substrate surface incurs damages on the crystal structure of the substrate. Additionally, for a semiconductor device with a line width less than 0.25 micron, stress is concentrated at the sharp corner of the shallow trench. A higher stress is thus resulted with the shallow trench isolation structure than the isolation structure formed by the traditional local oxidation of silicon, causing a crystal lattice dislocation is generated n the substrate. The conditions mentioned in the above would lead to a current leakage of the device.